Enabling circuit design using FinFETs through close ecosystem collaboration

Author

Sheu, Bing J. ; Chih-Sheng Chang ; Yen-Huei Chen ; Ken Wang ; Kuo-Ji Chen ; Yung-Chow Peng ; Li-Chun Tien ; Ming-Hsiang Song ; Hou, Chunping ; Sun, Jack Y.-C ; Chenming Hu

Author_Institution

TSMC, Hsinchu, Taiwan

fYear

2013

fDate

12-14 June 2013

Abstract

Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes key issues in enabling circuit design using FinFETs and how to address them effectively.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit design; 3D FinFET; EDA vendors; FinFET circuit; IP vendors; circuit design; design houses; double-patterning lithography; ecosystem collaboration; ecosystem design; fabrication foundry; packaging vendors; performance-power-area enhancement; planar CMOS; size 20 nm; CMOS integrated circuits; Doping; FinFETs; Integrated circuit modeling; Logic gates; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578741

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=630076