Title :
A 20nm 0.6V 2.1µW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme
Author :
Fujiwara, H. ; Yabuuchi, M. ; Morimoto, Masayuki ; Tanaka, Kiyoshi ; Tanaka, Mitsuru ; Maeda, Noboru ; Tsukamoto, Yuya ; Nii, Koji
Author_Institution :
Renesas Electron. Corp., Tokyo, Japan
Abstract :
For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 μW/MHz active power and 82% leakage power reduction.
Keywords :
SRAM chips; interleaved storage; system-on-chip; SRAM; SoC products; hierarchical bit-line scheme; hierarchical bitline scheme; interleave word-line scheme; interleave wordline; power reduction; size 20 nm; voltage 0.6 V; Bit error rate; Leakage currents; Low voltage; MOSFET; Power measurement; Random access memory; System-on-chip;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
