Title :
Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias
Author :
Yamamoto, Yusaku ; Makiyama, Hideki ; Shinohara, Hirofumi ; Iwamatsu, Takanori ; Oda, Hidekazu ; Kamohara, Shiro ; Sugii, Nobuyuki ; Yamaguchi, Yoshio ; Mizutani, Tomoko ; Hiramoto, Toshiro
Author_Institution :
Low-power Electronics Association & Project (LEAP), West7, 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, JAPAN
Abstract :
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVµm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Keywords :
Capacitance; Junctions; Logic gates; MOS devices; Random access memory; Transistors; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4673-5531-5
