• DocumentCode
    630090
  • Title

    Dual-VCC 8T-bitcell SRAM Array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range

  • Author

    Kulkarni, Jitendra ; Khellah, Muhammad M. ; Tschanz, James ; Geuskens, Bibiche ; Jain, R. ; Kim, Sungho ; De, Vivek

  • Author_Institution
    Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
  • fYear
    2013
  • fDate
    12-14 June 2013
  • Abstract
    A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. VMIN limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-VMIN. Measurements show 130-270mV lower VMIN with 27-46% lower power at 0.4-1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.
  • Keywords
    CMOS memory circuits; SRAM chips; energy conservation; voltage regulators; CMOS; SRAM array; energy-efficient operation; voltage regulator; Arrays; Boosting; CMOS integrated circuits; Delays; Energy efficiency; Random access memory; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2013 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-5531-5
  • Type

    conf

  • Filename
    6578755
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=630090