Title :
High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions
Author :
Hashemi, Pouya ; Kobayashi, Masato ; Majumdar, Angshul ; Yang, Li A. ; Baraskar, Ashish ; Balakrishnan, K. ; Kim, Wonhee ; Chan, Kap Luk ; Engelmann, Sebastian U. ; Ott, John A. ; Bedell, Stephen W. ; Murray, C.E. ; Liang, Shunlin ; Dennard, R.H. ; Sleigh
Author_Institution :
IBM Res., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
We demonstrate for the first time, Si1-xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance SiGe-channel PFETs with oncurrent ION = 1.1 mA/μm at off-current IOFF = 100 nA/μm and supply voltage VDD = 1 V, which is attributed to high hole source injection velocity vx0 exceeding 1 × 107 cm/s.
Keywords :
Ge-Si alloys; epitaxial growth; field effect transistors; high-k dielectric thin films; Si1-xGex; SiGe-channel PFET; electrostatic control; fin-and-gate dimensions; gate length; high hole source injection velocity; high-K/metal-gate stack; implant-free process; insulator trigate PFET; inversion oxide thickness; raised source-drain process; voltage 1 V; Electrostatics; Epitaxial growth; FinFETs; Logic gates; Silicon; Silicon germanium; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
