• DocumentCode
    63019
  • Title

    Verifying Correct Microarchitectural Enforcement of Memory Consistency Models

  • Author

    Lustig, Daniel ; Pellauer, Michael ; Martonosi, Margaret

  • Volume
    35
  • Issue
    3
  • fYear
    2015
  • fDate
    May-June 2015
  • Firstpage
    72
  • Lastpage
    82
  • Abstract
    Memory consistency models define the rules and guarantees about the ordering and visibility of memory references on multithreaded CPUs and systems on chip. PipeCheck offers a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification.
  • Keywords
    memory architecture; multi-threading; system-on-chip; PipeCheck; correct microarchitectural enforcement; memory consistency models; memory references; multithreaded CPU; systems on chip; Analytical models; Buffer storage; Load modeling; Microarchitecture; Pipelines; Program processors; Radio frequency; PipeCheck; computer architecture; formal verification; memory architecture; memory consistency model; processor microarchitecture;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2015.47
  • Filename
    7106405
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=63019