Modelling the PDF evolution in a CMOS inverter during switching

A model which facilitates the simulation of switching in a CMOS inverter, and a model for the associated PDF evolution, are proposed. The latter model is based on a Gaussian basis set. Simulation results, for the additive Gaussian white noise case, show, first, that the Gaussian assumption for the probability density function of the output jitter is valid at high input noise levels but with deviations from the Gaussian form for the propagation delay. Second, the output noise variance at a set time varies and is a maximum close to the midpoint between the high and low states. Third, the rms jitter of the output signal increases with the input rise time and the output load capacitance but decreases with increasing noise bandwidth. Fourth, the high correlation between the input and output signals leads to lower propagation delay jitter than expected.