A Reconfigurable Integrated Dispersive Delay Line (RI-DDL) in 0.13-/spl mu/m CMOS Process

This paper provides the theoretical analysis and physical implementation of a reconfigurable integrated dispersive delay line (RI-DDL) in the IBM 8RF 0.13-μm CMOS process. The RI-DDL employs a transversal filter structure, which is realized with the reverse gain port of a distributed amplifier. We successfully demonstrate that an RI-DDL is capable of achieving multiple nonuniform transmission line DDL transfer functions by altering the tap coefficients and polarities. The RI-DDL operates up to 4.5 GHz with 1.2-ns dispersion. We provide the experimental demonstration of the real time spectrum analysis (0.4-4 GHz) with the RI-DDL. Finally, we discuss the practical limitation of the proposed RI-DDL using the 0.13-μm CMOS process as well as the error bounds of the RI-DDL response due to discrete tap coefficient levels.