• DocumentCode
    631481
  • Title

    Advancement in Charge-Trap Flash memory technology

  • Author

    Tehrani, S. ; Pak, Jiwoo ; Randolph, Mark ; Yu Sun ; Haddad, Sandro ; Maayan, Eduardo ; Betser, Yoram

  • Author_Institution
    Spansion, Inc., Sunnyvale, CA, USA
  • fYear
    2013
  • fDate
    26-29 May 2013
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    Charge-trap Flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit® charge-trap technology has been the industry benchmark for NOR Flash for more than a decade, spanning six generations of scaling. More recently Heterogeneous Charge Trap (HCT)™ NAND Flash as well as embedded Charge Trap (eCT)™ NOR Flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3D charge-trap Flash will emerge and further extend the density-growth trend.
  • Keywords
    NOR circuits; flash memories; 3D charge-trap flash; HCT; NOR flash; eCT; embedded charge trap; flash memory technology; heterogeneous charge trap; industry benchmark; planar cell structures; two-bits-per-cell MirrorBit technology; Computer architecture; Flash memories; Industries; Interference; Logic gates; Microprocessors; Nonvolatile memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Workshop (IMW), 2013 5th IEEE International
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    978-1-4673-6168-2
  • Type

    conf

  • DOI
    10.1109/IMW.2013.6582082
  • Filename
    6582082