D2. Testing of 1.5 Bit per Stage Pipelined Analog to Digital Converter: 5 Bits Case Study

Nowadays, Analog to Digital converters are the main building blocks of mixed analog/digital signal circuits, hence testing ADC circuits has become mandatory. The pipelined Analog-to-Digital Converter (PADC) is widely used with its famous 1.5 bit/stage architecture. In this paper, a low-cost test is developed for a 5 bit PADC. The 5 bits PADC consists of 3-stage (1.5 bit/stage) PADC followed by a 2 bit flash ADC. Then, the digital output of the 4-stage PADC is followed by its time alignment and Digital Error Correction (DEC) circuits. They are based on a 90 nm CMOS technology. It is proved that only six DC test values can detect 96.3% of catastrophic faults in the fault set. An extra analog pin is required in order to achieve 100% fault coverage. The Eldo simulator provided by Mentor Graphics was used in the analysis.