VLSI design of parallel sorter based on modified PCM algorithm and Batcher´s odd-even mergesort

Data sorting is an important process in digital signal processing. There were many researches related to data sorting, two of them were about partition and concurrent merging (PCM) algorithm and Batcher´s odd-even mergesort network. PCM algorithm will decompose the data in several groups and sort them in two phases, quicksort and mergesort. We captured and modified the idea of PCM algorithm by eliminating unnecessary processes which can be handled directly by Batcher´s odd-even mergesort architecture. VLSI design of this parallel sorter is low complexity. It has 2k+1 clock cycles latency, which k represents the number of iterative steps for each kind of sorter block (odd or even). This design has been synthesized for FPGA Altera Cyclone II EP2C35F672C6 as target board.