DocumentCode
632975
Title
Impact of control flow blocks granularity on custom processor design time
Author
Ivosevic, Danko ; Sruk, Vlado
Author_Institution
Dept. of Electron., Microelectron., Comput. & Intell. Syst., Univ. of Zagreb, Zagreb, Croatia
fYear
2013
fDate
20-24 May 2013
Firstpage
863
Lastpage
868
Abstract
One of the key issues for system level design topic is the design time. This paper describes custom processor design tool as part of C-to-hardware flow and analyses its design time. The flow starts with C code specification and ends with FPGA implementation. The way the C code is processed has impact on the flow execution time. The implemented C code processing results with Control Flow Graph (CFG), and large control flow code blocks severely prolong the overall design time. Between two possibilities for design time improvement, variations in their granularities are chosen over tool internal algorithm and data structures optimizations. For 32-point DCT test case the results show huge design time decrease at the expense on the design quality: implementation resource occupation and execution time.
Keywords
discrete cosine transforms; field programmable gate arrays; integrated circuit design; 32-point DCT test case; C code specification; C-to-hardware flow; CFG; FPGA implementation; control flow blocks granularity; control flow graph; custom processor design time; data structures optimizations; design quality; execution time; flow execution time; resource occupation; system level design topic; tool internal algorithm; Algorithm design and analysis; Computer architecture; Discrete cosine transforms; Field programmable gate arrays; Optimization; Registers; Schedules;
fLanguage
English
Publisher
ieee
Conference_Titel
Information & Communication Technology Electronics & Microelectronics (MIPRO), 2013 36th International Convention on
Conference_Location
Opatija
Print_ISBN
978-953-233-076-2
Type
conf
Filename
6596378
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