Optimal Vth window in endurance and retention enhancement of MLC flash

Author

Ko Chen Hsien ; Kuo Shuen Chao ; Yi Heng Chen

Author_Institution

Quality Div., Powerchip Technol. Corp., Hsinchu, Taiwan

fYear

2013

fDate

15-19 July 2013

Firstpage

650

Lastpage

653

Abstract

In FLASH memory, Multi-level Chip (MLC) allowed increased storage capacity without increasing the die size, therefore it was cost-per-bit reduction for any given fabrication technology. Multi-level product needs requirement of a smaller Vth distribution and less noise margins between levels. A wider Vth window is associated with higher programming voltage and higher electric fields results in more disturb in reliability. In this paper, according to failure analysis result optimization of MLC Vth window to enhance the reliability of retention and Endurance test was studied on 40nm Multi-Level Chip Flash cells.

Keywords

failure analysis; flash memories; semiconductor device reliability; FLASH memory; MLC flash; cost-per-bit reduction; die size; electric fields; endurance test; fabrication technology; failure analysis; multilevel chip flash cells; multilevel product; optimal Vth window; programming voltage; storage capacity; Accuracy; Failure analysis; Flash memories; Integrated circuits; Optimization; Programming; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the

Conference_Location

Suzhou

ISSN

1946-1542

Print_ISBN

978-1-4799-1241-4

Type

conf

DOI

10.1109/IPFA.2013.6599244

Filename

6599244