Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators

Process variation has an increasingly dramatic effect on delay and power as process geometries shrink. Even if the amount of variation remains the same as in previous generations, it accounts for a greater percentage of process geometries as they get smaller. So an accurate prediction of path delay and power variability for real digital circuits in the current technologies is very important; however, its main drawback is the high runtime cost. In this paper, we present a new fast EDA tool which accelerates Monte Carlo based statistical static timing analysis (SSTA) for complex digital circuit. Parallel platforms like Message Passing Interface and POSIX^® Threads and also the GPU-based CUDA platform suggests a natural fit for this analysis. So using these platforms, Monte Carlo based SSTA for complex digital circuits at 32, 45 and 65 nm has been performed. and of the pin-to-output delay and power distributions for all basic gates are extracted using a memory lookup from Hspice and then the results are extended to the complex digital circuit in a hierarchal manner on the parallel platforms. Results show that the GPU-based platform has the highest performance (speedup of 19×). The correctness of the Monte Carlo based SSTA implemented on a GPU has been verified by comparing its results with a CPU based implementation.