A reduced-sample-rate 2–2–0 MASH-delta-sigma-pipeline ADC architecture

In this paper, a reduced-sample-rate 2-2-0 delta-sigma-pipeline analog-to-digital converter (ADC) is presented. The proposed architecture offers the possibility of implementing the reduced-sample-rate structure on higher order modulator without having stability or digital-to-analog converter (DAC) linearity problems. By the presented implementation approach some digital filters are eliminated, saving power at the digital part of the ADC. Implementing the reduced-sample rate structure on 2-2-0 MASH delta-sigma ADC with the OSR of 8, causes the 8-bit pipeline quantizer to work two times lower than the overall frequency at the expense of 1.5dB losses in SNR, and this is rewarding in high bandwidth applications. System level simulation using MATLAB/SIMULINK verifies the usefulness of the presented structure and 70dB SNR is achieved after the first decimation.