Title :
A very low OSR 90nm 1MS/s incremental ΣΔ ADC
Author :
Cavallo, D. ; De Matteis, M. ; Ronchi, M. ; Leggeri, G. ; Baschirotto, A.
Author_Institution :
Dept. of Phys. G. Occhialini, Univ. of Milan Bicocca, Milan, Italy
Abstract :
A calibration free, high resolution second-order multichannel Incremental A-to-D-Converter with multi-level quantizer is presented. The system is designed for biomedical application and combines the advantages of low oversampling ratio with SC design solution, like multi bit topology and accurate opamp design. An optimal decimation filter to minimize the weighted sum of thermal and quantization noise is used. In this paper is presented the schematic level implementation of the system in a 1.2 V 90 nm CMOS Technology and the preliminary simulation shows a 56.4 dB signal-to-noise-distortion within a 500 kHz bandwidth at a 16 MHz sample frequency.
Keywords :
CMOS integrated circuits; biomedical electronics; filtering theory; operational amplifiers; sigma-delta modulation; SC design solution; bandwidth 500 kHz; biomedical application; frequency 16 MHz; high resolution second-order multichannel incremental A-to-D-converter; low oversampling ratio; multibit topology; multilevel quantizer; opamp design; optimal decimation filter; quantization noise; schematic level implementation; signal-to-noise-distortion; size 90 nm; thermal noise; very low OSR incremental ΣΔ ADC; voltage 1.2 V; weighted sum minimization; Bandwidth; Clocks; Dynamic range; Modulation; Noise; Power demand; Topology; Analog-to-Digital conversion; CMOS analog integrated circuit; Incremental ΣΔ converter; Switched-Capacitor circuit;
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on
Conference_Location :
Villach
Print_ISBN :
978-1-4673-4580-4
DOI :
10.1109/PRIME.2013.6603106
