Random interleaved pipeline countermeasure against power analysis attacks

Author

Menicocci, Renato ; Trifiletti, A. ; Trotta, Fabrizio

Author_Institution

Fondazione Ugo Bordoni, Rome, Italy

fYear

2013

fDate

24-27 June 2013

Firstpage

145

Lastpage

148

Abstract

An RTL countermeasure intended to protect the AddRoundKey and SubByte steps of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on first order CPA attacks confirmed the effectiveness of the proposed countermeasure, especially in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the absolute value of correlation function is embedded in the measured noise floor and there are no peaks able to reveal the encryption key.

Keywords

coprocessors; correlation methods; cryptography; field programmable gate arrays; AES encoding coprocessor; AddRoundKey steps; DPA attacks; FPGA; RTL countermeasure; SBOX output; SubByte steps; absolute value; advanced encryption standard; correlation power analysis; differential power analysis attacks; encryption key; first order CPA attacks; noise floor; power curves; random interleaved pipeline countermeasure; Algorithm design and analysis; Correlation; Cryptography; Field programmable gate arrays; Logic gates; Pipelines; Registers; AES; CPA; DPA; FPGA; RTL countermeasure; Side Channel Attack;

fLanguage

English

Publisher

ieee

Conference_Titel

Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on

Conference_Location

Villach

Print_ISBN

978-1-4673-4580-4

Type

conf

DOI

10.1109/PRIME.2013.6603113

Filename

6603113