Optimal deployment of shadowed registers in systems with serial clock distribution

Digital sections in several high-precision mixed systems operate at a relatively low frequency, allowing the trading of speed for the mitigation of switching noise and power distribution problems. While the serial clock distribution potentially solves most of these problems, the standard library cells and synthesis tools do not provide much, if any support for the serial clock tree implementation. In our work we propose the necessary design flow modification and seek the optimal clock signal allocation for the deployment of shadowed registers subject to timing constraints and minimal area overhead.