Analysis and modeling of minority carrier injection in deep-trench based BCD technologies

This paper proposes a methodology for circuit simulation of parasitic effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. An equivalent circuit is used containing pre-calculated macro models for the injecting diode, the substrate of the chip and the sensitive diode. The macro models are generated by means of TCAD simulations which determine the carrier density distribution in the substrate. The carrier density in the substrate at the sensitive pn-junction is directly related to the parasitic current of the device. The results of the simulations are verified by test chip measurements.