S-parameter models for transient simulation in Verilog-A

This work presents a new method to model analog modules for transient simulations with their S-parameters and DC behavior. The model can be used for verification of analog circuits in a system simulation where the modeling is necessary to speed up transient simulations in analog domain for systems like Sigma Delta modulators (SDM) or DC/DC converters. The model includes circuitry to separate DC from AC in transient simulations to test various distortions on system level, like the power supply rejection. It is functional and shows high speed up for certain simulations.