A JTAG based 3D DfT architecture using automatic die detection

3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues including the test at all 3D manufacturing levels: pre, mid, and post bond levels. In this paper we propose an automatic die-detection mechanism able to detect the presence of upper and lower dies, and its integration within a JTAG based 3D test architecture. 3D die-detectors permit the optimization of the overall 3D test architecture: making it usable at all stacking levels without requiring a configuration step. This paper presents also synthesis results of the proposed test architecture with die-detectors.