A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation

In extracellular neural recording experiments, spike detection is an important step for information decoding of neuronal activities. An ASIC implementation of detection algorithms can provide substantial data-rate reduction and facilitate wireless operations. In this paper, we present a 16-channel neural spike detection ASIC. The chip takes raw data as inputs, and outputs three data streams simultaneously: field potentials down sampled at 1.25 KHz, band-pass filtered neural data, and spiking probability maps sampled at 40 KHz. The functionality and the performance of the chip have been verified in both in-vivo and benchtop experiments. Fabricated in a 0.13 μm CMOS process, the chip has a peak power dissipation of 85 μW per channel and achieves a data-rate reduction of 98.44%.