A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique

Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The core of this paper consist of the introduction of a novel and high performance design of an 8×8 multiplier using ancient Indian mathematics called Vedas. We have presented three different designs of the 8×8 Vedic multiplier using the CMOS technology, PTL and finally concoct the Vedic Multiplier using the Multi-Threshold Voltage CMOS (MTCMOS) and proved that the MTCMOS implementation of Vedic Multiplier is the best among all the implementations. The multiplier and the adder-subtractor units used for the implementation of Vedic multiplier are adopted from ancient methodology of India mathematics called as Vedas. The use of Vedas not only abates the carry propagation taking place from lsb to msb but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power than any other type of multipliers in the literature. The functionality of all the three designs and there PDP and total power consumptions at two different frequencies and three different voltages were calculated on tanner EDA 13.0v. The proposed MTCMOS implementation of Vedic multiplier is up to 24.55% power efficient and about 97.54% speedy as compared to the conventional CMOS implementation of Vedic multiplier.