DocumentCode :
63755
Title :
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver
Author :
Kaviani, K. ; Amirkhany, A. ; Huang, Chao ; Phuong Le ; Beyene, Wendemagegnehu T. ; Madden, Chris ; Saito, Kazuyuki ; Sano, Ko ; Murugan, V.I. ; Kun-Yung Ken Chang ; Yuan, X.C.
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Volume :
48
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
636
Lastpage :
648
Abstract :
This paper describes a low-power receiver front-end in a bidirectional near-ground source-series terminated (SST) interface implemented in a 40-nm CMOS process, which supports low-common mode differential NRZ signaling up to 16-Gb/s data rates. The high-speed operation is enabled by utilizing a common-gate amplifier stage with replica transconductance impedance calibration that accurately terminates the channel in the presence of receiver input loading. The near-ground low-impedance receiver also incorporates common-mode gain cancellation and in-situ equalization calibration to achieve reliable data reception at 16 Gb/s with better than 0.4 mW/Gb/s power efficiency over a memory link with more than 15 dB loss at the Nyquist frequency.
Keywords :
CMOS integrated circuits; calibration; low-power electronics; operational amplifiers; radio transceivers; CMOS process; Nyquist frequency; SST interface; bidirectional near-ground source-series terminated interface; bit rate 16 Gbit/s; common-gate amplifier stage; common-mode gain cancellation; in-situ equalization calibration; low-common mode differential NRZ signaling; low-power receiver front-end; memory link; near-ground low-impedance receiver; near-ground receiver front-end; receiver input loading; replica transconductance termination calibration; size 40 nm; source-series terminated transceiver; Calibration; Gain; Impedance; Loading; Receivers; Transconductance; Voltage control; CTLE; Common-gate receiver; DFE calibration; SST transceiver; common-mode to differential gain suppression; offset cancellation; replica impedance calibration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2013.2242714
Filename :
6466428
Link To Document :
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