Title :
A compact model of VES-BJT device
Author :
Kuzmicz, Wieslaw ; Mierzwinski, Piotr
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
VES-BJT is a bipolar transistor fabricated in the VESTIC technology. Its physical structure differs from other state-of-the-art bipolar transistors: its emitter and collector junctions are not plane-parallel, its base is uniformly doped and the emitter and collector regions are identical. In this paper it is shown how to estimate theoretically the most important parameters of its compact model. Comparison with results of numerical simulation is included, advantages and shortcomings of VES-BJT are discussed.
Keywords :
bipolar transistors; numerical analysis; semiconductor device models; VES-BJT device; VESTIC technology; bipolar junction transistors; collector junctions; compact model; emitter junctions; numerical simulation; Analytical models; Bipolar transistors; Doping; Integrated circuit modeling; Junctions; Numerical models; VESTIC; bipolar transistor; compact model;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference
Conference_Location :
Gdynia
Print_ISBN :
978-83-63578-00-8
