Optimized architecture of high order CIC filters

Author

Pristach, Marian ; Pavlik, Marek ; Haze, J. ; Fujcik, Lukas

Author_Institution

Dept. of Microelectron., Brno Univ. of Technol., Brno, Czech Republic

fYear

2013

fDate

20-22 June 2013

Firstpage

263

Lastpage

266

Abstract

The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Keywords

C++ language; application specific integrated circuits; digital filters; field programmable gate arrays; C++ language; VHDL description; application specific integration circuits; automatic filter generation; cascaded integrator-comb digital filter structure; field programmable gate arrays; high order CIC filters; lower power consumption; optimized architecture; Application specific integrated circuits; Clocks; Computer architecture; Field programmable gate arrays; Interpolation; Power demand; Software; Hogenauer filter; application specific integration circuits; cascaded integrator-comb filters; hardware description language;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference

Conference_Location

Gdynia

Print_ISBN

978-83-63578-00-8

Type

conf

Filename

6613354