DocumentCode
637683
Title
Design space of twin gate junctionless vertical slit field effect transistors
Author
Barbut, Lucian ; Jazaeri, Farzan ; Bouvet, D. ; Sallese, Jean-Michel
Author_Institution
Inst. of Electr. Eng., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
fYear
2013
fDate
20-22 June 2013
Firstpage
393
Lastpage
396
Abstract
In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs.
Keywords
field effect transistors; optimisation; JL VeSFET; drain induced barrier lowering; intrinsic off-current account; optimization; subthreshold swing; ultrathin body twin gate junctionless vertical slit field effect transistor; Doping; Electric potential; Field effect transistors; Logic gates; Nanowires; Silicon; DIBL; Junctionless; SCE; VeSFET; design space;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference
Conference_Location
Gdynia
Print_ISBN
978-83-63578-00-8
Type
conf
Filename
6613381
Link To Document