Title :
Heavily doped junctionless vertical slit FETs with slit width Below 20 nm
Author :
Barbut, Lucian ; Jazaeri, Farzan ; Bouvet, D. ; Sallese, Jean-Michel
Author_Institution :
Inst. of Electr. Eng., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
Abstract :
This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.
Keywords :
field effect transistors; heavily doped semiconductors; N-type devices; SOI substrates; Si; doping density; heavily doped junctionless vertical slit FET; slit width; twin gate junctionless vertical slit field effect transistors; Doping; Fabrication; Field effect transistors; Integrated circuits; Logic gates; Metals; Silicon; Junctionless; SOI; VeSFET; diffusion doping; n-type transistor; phosphorous; titanium; twin gate;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference
Conference_Location :
Gdynia
Print_ISBN :
978-83-63578-00-8
