A low complexity frequency-domain parallel demodulation structure combining matched filter with timing synchronization

For high-speed satellite communication system, the symbol rate of the modulated signal is usually high. However, the reliable working clock frequency of the commonly used digital processing chips is relatively lower, thus we should use parallel demodulation structure to achieve high-speed demodulation. A frequency-domain parallel demodulation structure combining matched filter with timing synchronization is proposed by analyzing the traditional demodulation structure based on FFT. The structure can decrease the output data rate of the matched filter, thus reducing the implementation complexity. In addition, a timing error calculation and amendment algorithm for the improved structure is proposed by illustrating its computational process and implementation architecture. The bit error rate of the proposed structure is simulated. The simulation results show that the structure has low implementation complexity and good performance such that it can meet the practical application requirements in high-speed satellite communication system.