Effect of drain bias on negative gate bias and illumination stress induced degradation in amorphous InGaZnO thin-film transistors

The effect of drain bias on negative gate bias and illumination stress (NBIS) stability of a-IGZO TFTs was investigated. The evolutions of transfer curves were explored with NBIS time using current-voltage characteristics measurements. In the initial stage (<;1000 s) of NBIS with grounded V_DS, transfer curves shifted negatively without subthreshold swing (S) degradation due to hole-trapping at the IGZO/gate insulator interface. On the other hand, on-current degradation occurred and was enhanced as NBIS duration increased. Results indicated that NBIS-induced defects were created above Fermi level energy (E_F). NBIS-induced states creation was enhanced under NBIS with positive drain bias (V_DS) of 40 V; however, it was found that NBIS-induced defects can be suppressed under negative V_DS bias of -60 V.