Using network calculus for analysing wired-wireless network on chip

Chip designs integrate hundreds and even thousands of smaller cores on a single chip. As such, the design and implementation of the underlying communication fabric is becoming a critical challenge. Network-on-Chips (NoCs) is a novel design paradigm that replaces the traditional bus-based networks to overcome the dual problems of scalability and latency. However, traditional NoC topologies, such as meshes or toruses, are still limited by high latency and excess power dissipation. Wired-Wireless networks-on-chips hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. For the evaluation of these proposed solutions, Our research focuses on the analytical prediction. It presents a study of hybrid NoC using Network Calculus (NC) theory. We aggregate the individual temporal properties of each component given in switch model to obtain the delay bound. Second we apply theses formulas to calculate the maximum end-to-end delay. This helps to specify the best physical and logical characteristics that can achieve enhanced performances.