• DocumentCode
    639324
  • Title

    A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

  • Author

    Annamalai, Arunachalam ; Rodrigues, Rance ; Koren, Israel ; Kundu, Sandip

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
  • fYear
    2013
  • fDate
    7-11 Sept. 2013
  • Firstpage
    133
  • Lastpage
    144
  • Abstract
    The importance of dynamic thread scheduling is increasing with the emergence of Asymmetric Multicore Processors (AMPs). Since the computing needs of a thread often vary during its execution, a fixed thread-to-core assignment is sub-optimal. Reassigning threads to cores (thread swapping) when the threads start a new phase with different computational needs, can significantly improve the energy efficiency of AMPs. Although identifying phase changes in the threads is not difficult, determining the appropriate thread-to-core assignment is a challenge. Furthermore, the problem of thread reassignment is aggravated by the multiple power states that may be available in the cores. To this end, we propose a novel technique to dynamically assess the program phase needs and determine whether swapping threads between core-types and/or changing the voltage/frequency levels (DVFS) of the cores will result in higher throughput/Watt. This is achieved by predicting the expected throughput/Watt of the current program phase at different voltage/frequency levels on all the available core-types in the AMP. We show that the benefits from thread swapping and DVFS are orthogonal, demonstrating the potential of the proposed scheme to achieve significant benefits by seamlessly combining the two. We illustrate our approach using a dual-core High-Performance (HP)/Low-Power (LP) AMP with two power states and demonstrate significant throughput/Watt improvement over different baselines.
  • Keywords
    multiprocessing systems; power aware computing; processor scheduling; AMP; DVFS; asymmetric multicore processors; computational needs; dual-core high-performance AMP; dual-core low-power AMP; dynamic thread scheduling; energy efficiency improvement; fixed thread-to-core assignment; frequency levels; multiple power states; opportunistic prediction-based thread scheduling; phase change identification; thread swapping; throughput maximization; voltage levels; watt maximization; Dynamic scheduling; Estimation; Instruction sets; Message systems; Multicore processing; Radiation detectors; Throughput; adaptive processor; core customization; heterogeneous multi-core processor; instruction-level parallelism; single-thread performance; superscalar; thread migration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on
  • Conference_Location
    Edinburgh
  • ISSN
    1089-795X
  • Print_ISBN
    978-1-4799-1018-2
  • Type

    conf

  • DOI
    10.1109/PACT.2013.6618804
  • Filename
    6618804