• DocumentCode
    639335
  • Title

    Exposing ILP in custom hardware with a dataflow compiler IR

  • Author

    Sangmin Seo ; Jun Lee ; Gangwon Jo ; Jaejin Lee

  • Author_Institution
    ManyCoreSoft, Seoul, South Korea
  • fYear
    2013
  • fDate
    7-11 Sept. 2013
  • Firstpage
    411
  • Lastpage
    412
  • Abstract
    In this paper, we address the effect of the work-group size on the performance of OpenCL kernels. We propose a profiling-based algorithm that finds a good work-group size, in terms of performance, for the target multicore CPU architecture. Our algorithm reduces misses in the private L1 data cache and achieves load balancing between cores. It exploits the polyhedral model to estimate the working-set size and the number of cache misses for a parameterized work-group size of the OpenCL kernel. Based on the profiling information, it heuristically searches the space of parameterized work-group sizes. Our virtually-extended index space helps to increase the probability to find a better work-group size. We implement our work-group size selection algorithm as a development tool that consists of a code generator and a search library. The code generator extracts the polytope of each memory reference from the kernel code and generates a function that simplifies polytopes using the run-time information and invokes search library routines. The search library calculates the working-set size using the polytopes and finds a proper work-group size. We evaluate our approach using 31 OpenCL kernels on four different multicore CPUs. We compare its accuracy and search time to those of an exhaustive search method. Experimental results show that our tool is, on average, 1566 times faster than the exhaustive search and selects a work-group size whose performance is the same as or comparable to that of the exhaustive search.
  • Keywords
    cache storage; multiprocessing systems; probability; program compilers; resource allocation; search problems; software libraries; OpenCL kernels; automatic OpenCL work-group size selection algorithm; code generator; development tool; exhaustive search method; kernel code; load balancing; memory reference; multicore CPU architecture; parameterized work-group size; polyhedral model; polytopes; private L1 data cache misses; probability; profiling information; profiling-based algorithm; run-time information; search library; virtually-extended index space; working-set size; Kernel; Search problems; Tin; dark silicon; dataflow; high-level synthesis; instruction level parallelism;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on
  • Conference_Location
    Edinburgh
  • ISSN
    1089-795X
  • Print_ISBN
    978-1-4799-1018-2
  • Type

    conf

  • DOI
    10.1109/PACT.2013.6618834
  • Filename
    6618834