DocumentCode
639616
Title
Validating EAST-ADL Timing Constraints Using UPPAAL
Author
Suryadevara, Jyotsna
Author_Institution
Malardalen Real-Time Res. Centre (MRTC), Malardalen Univ. (MDH), Vasteras, Sweden
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
268
Lastpage
275
Abstract
Systematic and formal development approaches for safety- and mission-critical systems are of increasing importance. These systems are often implemented as periodically triggered control systems, to ensure deterministic and analyzable timing behavior. However, integrating timing `constraints´ in the development process remains a challenging task. For instance, these constraints should be formally verified as consistent as well as feasible with respect to the system design. In this paper, we present a timed automata based validation approach for EAST-ADL timing constraints for periodic control systems. The constraints are specified using CCSL - the Clock Constraint Specification Language, and transformed into timed automata, to enable formal verification with UPPAAL model-checker. The resulting timed automata specification can be simulated and verified for the formal validation of the timing constraints. Further, the transformed specification model can be easily integrated with the corresponding model of the actual system design, also specified in CCSL, thus extending verification aspects. The proposed approach is demonstrated using the timing constraints for an Anti-lock Braking System (ABS) example.
Keywords
automata theory; braking; control engineering computing; formal specification; mechanical variables control; periodic control; program verification; specification languages; ABS; CCSL; EAST-ADL timing constraints; East-ADL timing constraint validation; UPPAAL model-checker; antilock braking system; clock constraint specification language; deterministic analyzable timing behavior; formal development approach; formal validation; formal verification; mission-critical system; periodically triggered control system; safety-critical system; system design; systematic approach; timed automata specification simulation; timed automata specification verification; timed automata-based validation approach; Automata; Clocks; Jitter; Semantics; Synchronization; Unified modeling language; CCSL; UPPAAL; embedded systems; real-time systems; timed automata; timing constraints; verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Engineering and Advanced Applications (SEAA), 2013 39th EUROMICRO Conference on
Conference_Location
Santander
Type
conf
DOI
10.1109/SEAA.2013.46
Filename
6619521
Link To Document