DocumentCode :
640051
Title :
Codes for network switches
Author :
Zhiying Wang ; Shaked, Omer ; Cassuto, Yuval ; Bruck, Jehoshua
Author_Institution :
Electr. Eng. Dept., California Inst. of Technol., Pasadena, CA, USA
fYear :
2013
fDate :
7-12 July 2013
Firstpage :
1057
Lastpage :
1061
Abstract :
A network switch routes data packets between its multiple input and output ports. Packets from input ports are stored upon arrival in a switch fabric comprising multiple memory banks. This can result in memory contention when distinct output ports request packets from the same memory bank, resulting in a degraded switching bandwidth. To solve this problem, we propose to add redundant memory banks for storing the incoming packets. The problem we address is how to minimize the number of redundant memory banks given some guaranteed contention resolution capability. We present constructions of new switch memory architectures based on different coding techniques. The codes allow decreasing the redundancy by 1/2 or 2/3, depending on the request specifications, compared to non-coding solutions.
Keywords :
memory architecture; minimisation; network coding; packet switching; redundancy; telecommunication network routing; coding techniques; contention resolution capability; data packet routing; degraded switching bandwidth; input ports; memory contention; multiple memory banks; network switch; output ports; packet storage; redundant memory banks; switch fabric; switch memory architectures; Decoding; Encoding; Ports (Computers); Redundancy; Systematics; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Theory Proceedings (ISIT), 2013 IEEE International Symposium on
Conference_Location :
Istanbul
ISSN :
2157-8095
Type :
conf
DOI :
10.1109/ISIT.2013.6620388
Filename :
6620388
Link To Document :
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