OpenCores® a robust complex network

The hardware development, in FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit), is benefitted by OpenCores. This is the world´s largest community for development of cores (blocks of logic and data for hardware implementation) as open source. In this work, the VHDL (Very High Speed Integrated Circuits Hardware Description Language) cores are inspected individually, using them with its parts to form a complex network. Then four network parameters are analyzed: clustering coefficient, mean geodesic distance, degree distribution, betweenness centrality, besides time evolution, and behavior in front of random attacks. The obtained results evidence a network of technological characteristics with small-world effect. This is not scale-free network, although have a similar temporary evolution but only upon average. The network is robust because holds its capabilities when eliminating a great part of its nodes by means of random attacks, and due to its betweenness centrality and degree distribution, that they assure its robustness against directed attacks.