Predicting the noise floor at the output of a memoryless piecewise-linear nonlinearity driven by a digital delta-sigma modulator

Digital Delta-Sigma Modulators (DDSMs) are widely used in fractional-N frequency synthesizers. Much design effort is typically expended to smooth and shape the DDSM´s output spectrum. This good work can be undone by nonlinearities in the phase-locked loop (PLL) which cause the noise floor resulting from the DDSM to rise, thereby degrading the inband phase noise performance of the system. This paper characterizes the noise floor produced by a memoryless asymmetric piecewise-linear nonlinearity, which typically results from a mismatch between the up and down currents in the charge pump.