Efficient switching scheme using multiple shared memories

A novel switching scheme using multiple shared memories is proposed. It has low implementation complexity and ideal performance for both uniform traffic and non-uniform traffic without speedup. The proposed algorithm assigns an output time for each incoming data according to its destination and distributes them into 2N shared memories that can be addressable by output time, where N is the number of input/output ports. Experimental results show that the proposed scheme has good performance for both uniform traffic and non-uniform traffic.