Fault scanning and repairing in processor based system using dynamic reconfiguration

In this paper, a new method of fault tolerance technique through dynamic reconfiguration is achieved in Processor based System. There involves two parts of technique Fault detection and Fault recover. First, a new reseeding architecture for scan based built - in self-set (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. A seed - selection algorithm is furthermore presented that, taking advantage of the multiphase architecture, manages to significantly reduce the number of the required seeds for achieving complete (100%) fault coverage. Then simple LDPC codes based on Euclidean geometries (EG-LDPC) are included to verify whether the TPG output is correctly fed to processor which is the circuit under test (CUT). The main goal of testing and diagnostic process of CUT is achieved by the mechanism of Roving Self-Testing Area (Roving STAR).This process takes place in self-test areas of FPGA without affecting normal system operation. By this way entire chip is tested by roving the STARs across FPGA. In case of occurrence of any fault the ORA gives the fail response to memory unit, then memory unit fed the correct output from LUT for particular clock cycle.