An energy recovery logic level countermeasure for power analysis attacks on AES

The chips designed for security related applications must be robust, to globally resist various types of attacks. Power analysis attacks are now becoming a significant threat to the exploitation of security in many devices. These attacks proficiently disclose the secret key information without much effort. Advanced Encryption Standard (AES) is a widely used symmetric cryptographic algorithm, which is also susceptible to such power attacks. In the proposed work, we have replaced the AddRoundKey block of AES with adiabatic 2N-2N2P logic. This countermeasure breaks the dependency between the power consumption trace and the secret key information. To validate its efficiency in counteracting against DPA we have compared with CMOS logic. In addition to the resistance offered against DPA attacks, this design lowers the overall power consumption as part of the energy consumed is recovered during each clock cycle.