Title :
Design methodologies for high density domain wall memory
Author_Institution :
Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.
Keywords :
cache storage; integrated circuit design; low-power electronics; random-access storage; design methodologies; embedded cache application; endurance; fast access time; high density domain wall memory; low standby power; multilevel cell capability; on-chip cache; retention; Arrays; Integrated circuit modeling; Magnetic heads; Magnetic tunneling; Resistance; Transistors; Domain wall memory; High density memory;
Conference_Titel :
Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on
Conference_Location :
Brooklyn, NY
Print_ISBN :
978-1-4799-0873-8
DOI :
10.1109/NanoArch.2013.6623035
