DocumentCode :
6414
Title :
Extraction of Gate Resistance in Sub-100-nm MOSFETs With Statistical Verification
Author :
Xuesong Chen ; Mu Kai Tsai ; Chih-Hung Chen ; Lee, Razak ; Chen, Daniel C.
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada
Volume :
61
Issue :
9
fYear :
2014
fDate :
Sept. 2014
Firstpage :
3111
Lastpage :
3117
Abstract :
This paper presents an improved z-parameter based approach to extract the gate resistance at low frequencies. The effectiveness of this approach, compared with other y-parameter based approaches, is verified using 430 samples fabricated in 40-, 55-, 90-, and 110-nm CMOS technology nodes. The influence of the nonquasi-static (NQS) effect, resulting from the distributed channel resistance, on the gate resistance extraction is studied, and the optimum processes are suggested to reduce the NQS effect. Finally, the extraction of the channel resistance in the lightly doped drain region is also presented.
Keywords :
CMOS integrated circuits; MOSFET; statistical analysis; CMOS technology node; MOSFET; NQS effect; distributed channel resistance; gate resistance extraction; lightly doped drain region; metal-oxide-semiconductor field-effect transistor; nonquasi-static effect; size 100 nm; size 110 nm; size 40 nm; size 55 nm; size 90 nm; statistical verification; y-parameter; z-parameter; Equivalent circuits; Frequency measurement; Logic gates; MOSFET; Noise; Resistance; Thermal noise; Distributed channel resistance; distributed poly-silicon gate resistance; gate contact resistance; gate resistance extraction; nonquasi-static (NQS) effect;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2014.2340871
Filename :
6868994
Link To Document :
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