A modified RCM for reversible watermarking with FPGA implementation

Reversible contrast mapping (RCM) is used in reversible watermarking (RW) for images as a simple integer transform applied on pair of pixels and their least significant bits (LSB) are used for data embedding. This paper first proposes some modifications on existing RCM technique for further performance improvement in terms of embedding rate and visual distortion. This is then followed by a hardware architecture implementation in field programmable gate array (FPGA) platform. For a cover image of size (32×32) and a watermark of 512 bit length, the proposed architecture consumes 7463 slices, 8344 slice flip-flop, 6592, 4-input LUTs and 5 BRAMs for watermark embedding at maximum clock frequency of 67.98 MHz.