An implementation of FFT processor

This paper introduced a FPGA design scheme of the Radix-2² in the realization of the FFT processor. This method with the SDF structure was considered to decrease the control complexity, increase the utilization factor of the butterfly. The numbers of storage and multiplier were reduced and nonstopping input data could be processed because of the pipeline architecture. At last the architecture was implemented with the Xilinx ISE development tool using VHDL and the balance of different aspects such as speed, resource and storage was tried. Experimentation shows that it is a feasible method to use R2² algorithm to realize FFT transform.