Reliability monitoring of digital circuits by in situ timing measurement

Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.