DocumentCode :
642618
Title :
Reliability monitoring of digital circuits by in situ timing measurement
Author :
Aryan, Naser Pour ; Georgakos, Georg ; Schmitt-Landsiedel, Doris
Author_Institution :
Tech. Univ. Muenchen, Munich, Germany
fYear :
2013
fDate :
9-11 Sept. 2013
Firstpage :
150
Lastpage :
156
Abstract :
Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.
Keywords :
circuit reliability; digital circuits; low-power electronics; time measurement; aging resistant circuitry; digital circuits; in situ timing measurement; low power technology; optimized design; power efficiency; reliability monitoring; remaining timing slack; size 65 nm; test circuit; Aging; Integrated circuit reliability; Logic gates; Monitoring; Temperature measurement; Temperature sensors; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on
Conference_Location :
Karlsruhe
Type :
conf
DOI :
10.1109/PATMOS.2013.6662168
Filename :
6662168
Link To Document :
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