A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults

Author

Possamai Bastos, Rodrigo ; Sill Torres, Frank ; Dutertre, J.-M. ; Flottes, M.-L. ; Di Natale, G. ; Rouzeyre, B.

Author_Institution

TIMA Lab., UJF, Grenoble, France

fYear

2013

fDate

9-11 Sept. 2013

Firstpage

157

Lastpage

163

Abstract

This work proposes a novel built-in current sensor for detecting transient faults of short and long duration as well as multiple faults in combinational and sequential logic. Unlike prior similar strategies, which are formed by pairs of PMOS and NMOS sensors, the proposed scheme is a single sensor connected to PMOS and NMOS bulks of the monitored logic. In comparison with existing transient-fault mitigation techniques, the paper presents very competitive results that indicate no performance penalty, and overheads of only 26 % in power consumption and 23 % in area.

Keywords

CMOS logic circuits; combinational circuits; electric sensing devices; fault diagnosis; sequential circuits; NMOS bulks; NMOS sensors; PMOS bulk; PMOS sensors; built-in current sensor; combinational logic; monitored logic; power consumption; pull-up-pull-down CMOS networks; sequential logic; single-built-in sensor; transient fault detection; transient-fault mitigation technique; CMOS integrated circuits; Circuit faults; Inverters; MOS devices; Monitoring; Transient analysis; Transistors; Built-in current sensors; concurrent detection; fault attacks; fault tolerance; security; soft errors; transient faults;

fLanguage

English

Publisher

ieee

Conference_Titel

Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on

Conference_Location

Karlsruhe

Type

conf

DOI

10.1109/PATMOS.2013.6662169

Filename

6662169