Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations

On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core architectures. However, there is still a need for efficient power-performance methodologies, since the interconnect power-envelope is really slim and cannot be neglected. Indeed, new power-aware design explorations in current and future multicore systems are needed. The possibility to use different router microarchitectural options and different routing algorithms to increase performance, combined with standard power-aware mechanisms, i.e. DVFS and Power Gating techniques, provides a huge design space to be explored. In this perspective, this paper presents a comparative analysis of different NoC routing algorithms combined with Dynamic Frequency Scaling (DFS).