Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.