A high dynamic range CMOS image sensor with a digital configurable logarithmic counter

Many kinds of high dynamic range (HDR) CMOS Image Sensors (CIS) have been reported, such as a multiple sampling, a multiple exposure technique, and so on. However, those techniques have some disadvantages of noise increasing, large power consumption, and huge chip area. In this paper, a new digital configurable logarithmic counter is described. Since the proposed scheme is easily implemented with a very simple technique, we can reduce power consumption and chip area drastically. Further, the logarithmic counter enhances the dynamic range (DR). The chip which has been fabricated using a 0.13um CIS process has an excellent SNDR at high speed sampling rate.