An LDO using stacked transistors on 65 nm CMOS

Author

Pashmineh, Sara ; Bramburger, Stefan ; Hongcheng Xu ; Ortmanns, Maurits ; Killat, Dirk

Author_Institution

Microelectron. Dept., Brandenburg Univ. of Technol., Cottbus, Germany

fYear

2013

fDate

8-12 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two pass transistors. The first pass transistor is controlled by the main error amplifier; the 2nd pass transistor is controlled by 2nd amplifier adjusting the division of the voltages between the two pass transistors. The paper presents circuit design and simulations results of a LDO with 500 mA output current using the 2.5 V transistors of the TSMC 65 nm CMOS low-power process technology.

Keywords

CMOS integrated circuits; amplifiers; integrated circuit design; voltage regulators; 2nd pass transistor; 3-stage error amplifiers; CMOS low-power process technology; GBW; LDO; circuit design; circuit simulations; current 500 mA; feedback loops; high voltage compatibility; load regulation; low drop-out voltage regulator; pass transistor stacking; size 65 nm; stability; stacked transistors; voltage 2.5 V; CMOS integrated circuits; CMOS technology; Feedback loop; Regulators; Transient response; Transistors; Voltage control; LDO; low drop-out voltage regulator; regulator; stacked transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2013 European Conference on

Conference_Location

Dresden

Type

conf

DOI

10.1109/ECCTD.2013.6662290

Filename

6662290